The present invention relates generally to semiconductor manufacturing and, more particularly, to a method and test structure for distinguishing between dopant and line width variation components.
The manufacturing of semiconductor devices may involve many process steps. For example, semiconductor fabrication typically involves processes such as deposition processes, etching processes, thermal growth processes, various heat treatment processes, ion implantation, photolithography, etc. Such processes may be performed in any of a variety of different combinations to produce semiconductor devices that are useful in a wide variety of applications.
In general, there is a constant drive within the semiconductor industry to increase the operating speed and efficiency of various integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds and efficiency. This demand for increased speed and efficiency has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors, as well as the packing density of such devices on an integrated circuit device. That is, many parameters of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor or the thinner the gate insulation layer, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
Modern field effect transistors comprise a gate electrode, a gate insulation layer, a source region and a drain region. When an appropriate voltage is applied to the gate electrode, a channel region is formed between the source region and the drain region and electrons (or holes) flow between the source region and drain region. The source and drain regions of such transistors are normally the same. For example, for an NMOS transistor, both the source and drain regions are formed by introducing an N-type dopant material, e.g., arsenic, into the semiconductor material. For a PMOS transistor, the source and drain regions are formed by introducing a P-type dopant material, e.g., boron, into the semiconductor material.
As device geometries continually decrease, the effects of small variations in fabrication parameters have an increasingly noticeable effect on the performance of the completed devices. During the formation of the source and drain regions, there is some variation in the number of atoms that are implanted in the region adjacent the channel region, which is commonly referred to as the halo region. Implant variations cause variations in the effective channel length of the transistors. Due to the small geometries being fabricated, variations as small as a few hundred atoms can have an appreciable effect on the performance of the device. For instance, the threshold voltage of the device may be impacted by variation in the implants in the halo region.
Another factor that may affect performance parameters of the transistor, such as threshold voltage, is the length of the gate electrode. Variation in the length affects the physical channel length of the device. FIG. 1 illustrates a typical roll-off curve 100 relating the threshold voltage to changes in length. Typically, target values for the nominal length are selected at value near L1 designated on the curve 100. The device roll-off is essentially flat for super-nominal and larger (i.e., greater than L1) devices.
Because it is difficult to distinguish between these various sources of variation, such as random dopant or random length variation, it is difficult to adjust design or process parameters to reduce the variation. Moreover, as the effects of such variation sources are causing an increasingly noticeable impact on the overall variation of the fabricated devices, the lack of effective process or design control techniques may potentially reduce the performance, and ultimately, the profitability of the devices.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the present invention described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the present invention. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.